Aiming at the high-speed data readout from the on-chip memory of the uncooled infrar ed detector,a low-latency sensitive amplifier for the on-chip memory of the un cooled infrare d detector is designed.As the pixel array of uncooled infrared detectors continu es to increase,the requirements for the on-chip memory of uncooled infrared det ectors are also higher,an d a higher-speed memory is needed for the internal data storage of the infrared detector. Reducing the delay time of the sensitive amplifier is a reliable method to incre ase the data tra nsmission speed.In this paper,the traditional cross-coupling structure of the s ensitive am plifier is improved.Compared with the traditional cross-coupling structure of t he sensitive amplifier,a completely complementary second-stage cross amplifying circuit is added,and an intermediate stage composed of NMOS is used to couple the two-stage operatio nal amplifier. The improved new sensitive amplifier can quickly and effectively amplify the vol tage difference on the bit line,and at the same time improve the problem of low sensitivity.The sensitive amplifier designe d in this pap er uses TSMC 65 nm process.Under the conditions of 5 V working volta ge and 100 mV bit l ine voltage difference,the simulation results show that the data readout delay i s only 25.19 ps.Compared with the cross-coupled sensitive amplifier,the readout del ay is reduced by 37.07%.At the sametime,under the simulation conditions of the full process angle,the ambie nt temperat ure is －45 ℃to 125 ℃,the delay simulation maximum value of the new sensitive amplifier is only 39 ps,and the minimum value is 17.1 ps.